With increase in complexity and/or integration of semiconductor devices, a channel length of a transistor has considerably decreased. Such a decrease in channel length entails a problem of sharply lowering the threshold voltage of the transistor, a so-called “short channel effect.” The short channel demands implantation of a relatively large amount of channel ions so as to maximize punch-through characteristics between a source and a drain region. In order to maximize the short channel effect, a recessed gate transistor, which has an increased channel length by forming recesses in a silicon substrate during the manufacture thereof, has recently drawn attention. This is often referred to as a “vertical trench transistor.”
FIG. 1 is a cross-sectional view illustrating a recessed gate transistor 100. Referring to FIG. 1, the recessed gate transistor 100 includes a silicon gate 50 insulated from a main body 30 by interposing a gate oxide layer 40 therebetween, and source regions 52, 54 formed in a surface of the main body 30 at both sides of the silicon gate 50. A metal layer 60 is deposited on and/or over the silicon gate 50 to form a contact. In addition, an insulating layer 45 is added to insulate the silicon gate 50 from the metal layer 60.
If the transistor lacks overlay margin between a trench in which the silicon gate 50 is formed and the contact in the metal layer 60, gate leakage current (IGSS), i.e., a gate-source current is deteriorated when drain-source short circuit occurs by applying a specific gate voltage to the transistor. In addition, if the contact pattern exhibits misalignment or inferior uniformity of critical dimension (CD), the overlay margin must be increased. This may extend a transistor pitch, causing an increase in drain-source on-state resistance (Rds-on) of a forward biasing MOSFET.